Embedded bridge interconnection may provide faster communication between processors and memory chips. Various dies may need to be attached to a substrate at the first level interconnection (FLI) to enable high performance computing (HPC). As dies continue to shrink to smaller dimensions, a finer pitch is generally needed between interconnect structures at the FLI level.
Providing a finer pitch for future computing devices may be challenging using present technologies. For example, presently, a mixed bump pitch between processor die and memory die, may make packaging and assembly very challenging and result in poor yield performance. FLI joint architecture that employs a solder paste printing (SPP) process may result in yield failures due to limitations to solder bump height and/or solder volume on the dies, which may result in non-contact opens and bump cracks, especially for smaller pitch areas of the FLI. Moreover, electromigration risk may be elevated due to copper (Cu) diffusion and organic solder preservative (OSP) surface finish used on a substrate side for FLI joint.